Exemplary embodiments of the present invention relate to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device with a gate pattern including a diffusion barrier layer and a metal silicide layer and a method for fabricating the semiconductor device.
Recent improvement in the integration degree of a semiconductor device has reduced the area of the semiconductor device. However, as the area is reduced, the resistance in a gate pattern and/or a word line increases, and therefore, the characteristics of the semiconductor device are deteriorated. This deterioration is a cause for concern. To address this concern, a method of reducing the resistance by forming a gate pattern and a word line of a metal silicide layer having a low resistance value has been considered.
Hereafter, a conventional method for forming a gate pattern and the concerns surrounding the method will be described.
FIG. 1A is a cross-sectional view illustrating a structure of a conventional gate pattern. As illustrated in the drawing, the gate pattern is formed by sequentially stacking a gate insulation layer 11, a conductive layer 12, a diffusion barrier layer 13, and a metal silicide layer 14 over a substrate 10. The gate pattern includes spacers 15 on its side walls and the gate regions between gate patterns are filled with an interlayer dielectric layer 16.
The gate insulation layer 11 is generally formed of an oxide layer, and the conductive layer 12 is generally formed of a polysilicon layer.
The metal silicide layer 14 reduces the resistance of a gate pattern or a word line, and it is generally formed of a nickel silicide (NiSi) layer formed from a reaction between a polysilicon layer and a nickel layer.
Herein, the metal silicide layer 14 is formed by sequentially forming a polysilicon layer and a metal layer over the diffusion barrier layer 13 and making the polysilicon layer react with the metal layer through a thermal treatment.
The diffusion barrier layer 13 is used to form the metal silicide layer 14 of a uniform thickness and prevent the metal included in the metal silicide layer 14 from being diffused into the conductive layer 12 under the diffusion barrier layer 13 during the formation of the metal silicide layer 14. Accordingly, the diffusion barrier layer 13 is interposed between the conductive layer 12 and the metal silicide layer 14.
Herein, the diffusion barrier layer 13 is generally formed to include a metal different from the metal included in the metal silicide layer 14. For example, when the metal silicide layer 14 is formed of a nickel silicide layer, the diffusion barrier layer 13 is formed by siliciding cobalt (Co) or titanium (Ti). In other words, the diffusion barrier layer 13 is formed of cobalt silicide (CoSi2) or titanium silicide (TiSi2).
However, there is concern that the diffusion barrier layer 13 is not sufficiently silicided due to a line width effect caused by the improvement in the integration degree of semiconductor devices. In particular, when the design rule is under approximately 40 nm, the diffusion barrier layer 13 including Co or Ti is scarcely silicided. Thus, the diffusion barrier layer 13 does not perform its function properly, and it may be contaminated with an impurity due to the Co or Ti during gate patterning.
Also, although the diffusion barrier layer 13 including Co or Ti is silicided, the Co or Ti characteristically requires a large amount of polysilicon during its silicidation process. In other words, a considerable amount of the polysilicon layer formed in the upper and lower portions of the diffusion barrier layer 13 is consumed and this affects the formation of the metal silicide layer 14 subsequently formed.
FIG. 1B shows a problem occurring in the course of performing a high-temperature process after the formation of a gate pattern according to the prior art. Herein, a metal silicide layer fused in the high-temperature process is marked with reference numeral ‘14A’ and referred to as a fused metal silicide layer 14A.
As described above, the diffusion barrier layer 13 including Co or Ti may experience a change in phase or volume due to a reaction, such as silicidation during the high-temperature process. In this case, the metal included in the diffusion barrier layer 13 or the fused metal silicide layer 14A may be diffused into the conductive layer 12 under the diffusion barrier layer 13 (see reference symbol ‘B’). In short, the diffusion barrier layer 13 does not properly perform its function.
Also, during the high-temperature process, a void (see reference symbol ‘A’) may be formed between the fused metal silicide layer 14A and the diffusion barrier layer 13.
For example, the fused metal silicide layer 14A formed of a nickel silicide layer has a melting point of approximately 950° C. At a temperature close to the melting point, the fused metal silicide layer 14A is liquefied. Herein, since the surface energy of the diffusion barrier layer 13 is low, the adhesion between the liquid-phase fused metal silicide layer 14A and the diffusion barrier layer 13 is decreased. Therefore, the fused metal silicide layer 14A is formed into a waterdrop shape and accordingly void A may be caused at the interface between the fused metal silicide layer 14A and the diffusion barrier layer 13. Herein, since the void A causes a vertical voltage drop, the performance of a semiconductor device is deteriorated due to an unbalanced vertical voltage.
The above-mentioned concerns may exist in all devices including a gate pattern using a metal silicide layer. In the present specification, the problems occurring when a gate pattern of a Dynamic Random Access Memory (DRAM) device is formed are described as an example. Although, the same problems may occur in the process of forming a gate electrode or a word line of a non-volatile memory device as well.